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Prime Minister Narendra Modi addressed gathering at SEMICON India 2026 in New Delhi, on September 17.
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News18•22-09-2026, 13:39
SEMICON India 2026: India's Semiconductor Ecosystem Expands Beyond Chip Design to AI & HPC
  • •SEMICON India 2026 showcased India's expanding semiconductor capabilities, moving beyond chip design to advanced packaging, AI, materials, equipment, and high-performance computing.
  • •The event highlighted indigenous computing technologies, including C-DAC's AUM HPC-AI Processor and RUDRA-AUM compute node, and application-specific chips for various sectors.
  • •RISC-V processors are a key focus, with C-DAC and InCore Semiconductors developing indigenous IP for high-performance and edge-AI applications.
  • •The exhibition featured integrated solutions like Aheesa Technology's indigenous internet connectivity device, powered by C-DAC's RISC-V processor and Vihan software.
  • •India's semiconductor ambition is supported by Semicon 2.0, a Rs 1,27,500 crore outlay, and initiatives like the DLI Scheme and Chips to Startup Programme to foster talent and design.

Key Questions Answered

SEMICON India 2026 took place at Yashobhoomi in New Delhi from September 17 to 19, 2026. Organized around the theme 'Silicon to Systems: Building the Ecosystem', the fifth edition featured over 600 exhibitors from 52 countries, highlighting capabilities across chip design, advanced packaging, artificial intelligence, materials, equipment, and high-performance computing.

The Union Cabinet approved Semicon 2.0 in July 2026 with an outlay of Rs 1,27,500 crore, expanding on the foundational goals of Semicon 1.0. This next phase focuses on six major areas: chip design, machines and materials, additional fabs, advanced packaging, research and development, and talent development.

India is expanding its semiconductor design workforce through the Design Linked Incentive (DLI) Scheme and the Chips to Startup (C2S) Programme. Through the ChipIN Centre, over one lakh engineers from more than 500 organizations have gained access to design tools and training, resulting in over 300 developed chip designs.